● AMD招募实习生（职位已更新2008024）

发信人: brittany (静水流深), 信区: job
标  题: AMD招募实习生（职位已更新2008024）
发信站: 饮水思源 (2008年04月24日12:59:28 星期四)

Notes 
•	Can work in office around 6 months, 3+ workdays per week.(Must)
•	Will get a full-time offer based on your performance
•	Read requirement carefully and do not repeat to apply
•	Internship period: late May----early Nov.
•	Written test and interview: early May 
•	send resume to Brittany.Zhang@AMD.com , marked with position and your 
name in email subject line.

ASIC Flow Design Engineer
Role and Chance
1.	Led by United States ASIC flow design manager to work with a world class te
am and learn to design and build multi-million-transistor next generation Grap
hics Processors. AMD U.S. ASIC flow design manager graduated from MIT and has 
more than 15 years of experience in ASIC field.  He is leading the U.S. ASIC f
low design team to develop the world’s leading edge ASIC flow for current and
 future process like 65nm, 45nm and beyond. 
2.	Gain design and automation skills in various aspects of the front-to-back e
nd ASIC design flow including: synthesis, netlisting, chip assembly, IP manage
ment, floorplanning, time budgeting, power grid design, and clocking methodolo
gy, among other areas. 

Skill and Experience Requirement
1.	Strong communication skills, analytical thinking skills; chip design backgr
ound, and coding skills are required.
2.	Must work well with others to define problems and solutions, but also work 
individually in the implementation phase.
3.	Master of Science Degree in Electrical Engineering, Computer Science, Compu
ter Engineering or foreign equivalent. 
4.	Coursework/experience in VLSI, logic design, timing, synthesis, layout, sof
tware design concepts; proficiency in shell/perl/tcl/python a plus. 
5.	Strong desire to learn about new design methodologies and chip technologies
.
6.	32+ flexible working hours per week; full time preferred.

Design Verification-HW/SW 
Role and Chance
1.	Work with the world top class graphic team to verify the next generation co
mputer graphic chips which will support future Microsoft DirectX 10 and beyond
. 
2.	Your job is to work closely with the ASIC designers to understand the archi
tecture of 3D graphics chip and functional block being designed; develop the r
eference model and testbench to ensure functional completeness. 
3.	Learn and help developing the advanced verification methodologies and flows
 for multi-million-gates ASIC design which is the most sophisticated design th
at you can ever touched. We offer you the opportunity and all the EDA resource
s. Challenge and prove yourself.

Skill and Experience Requirements 
1.	Master in CS or EE
2.	Solid Electronics background knowledge
3.	Good Digital Design skill and concept.
4.	Familiar with Verilog HDL coding and debugging tools.
5.	Familiar with Linux Environment 
6.	Expert in c/c++, Makefile and at least one of the script/shell programming(
Perl, Python, awk, sed etc.).
7.	Strong desire to learn new design methodologies.
8.	Experience with design verification methodologies. (plus) 
9.	Strong Interest on graphics and have some knowledges (Plus)
10.	Familiar with Verdi, PLI, SystemC, or Verilog (plus) 

Video performance verification
Role and Chance
1.	Work with world top class graphics/video design team to verification video 
performance, analysis performance data and help provide solution for next gene
ration product.
2.	Compose test plan and validation vectors to ensure performance design targe
t according to the design specification; perform formal verification on the de
sign; write test vectors for simulation and emulation; and develop test progra
ms. 

Skill and Experience Requirement
1.	Master in CS or EE
2.	Strong computer science background
3.	Solid C/C++ coding skills
4.	Solid video processing knowledge. Strong plus: MPEG2, MPEG4, H.263, H.264 o
r VC-1 codec developing experience
5.	Scripting/programming experience.
6.	Familiar with Linux environment
7.	Good communication skill, both Chinese and English
--
我看到我身边，他们都比我美；我看到我身后，时间都已枯萎。






※ 来源:·饮水思源 bbs.sjtu.edu.cn·[FROM: 210.13.97.168]

※ 修改内容:·brittany 于 04月24日13:09:37 修改本文·[FROM: 210.13.97.168]

※ 修改内容:·brittany 于 04月24日13:15:02 修改本文·[FROM: 210.13.97.168]